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.checkpatch.conf
View file @ a5442c30
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
--ignore=FILE_PATH_CHANGES --ignore=FILE_PATH_CHANGES
--ignore=GERRIT_CHANGE_ID --ignore=GERRIT_CHANGE_ID
--ignore=NOT_UNIFIED_DIFF --ignore=NOT_UNIFIED_DIFF
--ignore=STRLCPY
--ignore=PREFER_KERNEL_TYPES --ignore=PREFER_KERNEL_TYPES
--ignore=USLEEP_RANGE --ignore=USLEEP_RANGE
--kconfig-prefix=CFG_ --kconfig-prefix=CFG_
.devcontainer/Dockerfile.vscode 0 → 100644
View file @ a5442c30
FROM ubuntu:22.04
ENV DEBIAN_FRONTEND=noninteractive
RUN apt update && apt upgrade -y && apt-get install -y \
build-essential \
autoconf \
bc \
bison \
ccache \
clang \
lld \
cmake \
codespell \
device-tree-compiler \
expect \
flex \
gcc-aarch64-linux-gnu \
gcc-arm-linux-gnueabihf \
gcc-riscv64-linux-gnu \
gdb-multiarch \
gdisk \
gettext \
libncurses5 \
libssl-dev \
lsb-release \
python3 \
python3-pip \
python3-cryptography \
python3-pycodestyle \
python3-pycryptodome \
python3-pyelftools \
sudo \
uuid-dev \
wget \
curl \
git-core \
git-man \
git-email \
sudo \
nano \
vim \
openssh-client \
bash-completion
# Add non root user
RUN useradd -ms /bin/bash optee
RUN echo "optee ALL=(ALL) NOPASSWD: ALL" | tee -a /etc/sudoers
USER optee
.devcontainer/devcontainer.json 0 → 100644
View file @ a5442c30
{
"name": "optee-os-docker",
"build": {
"dockerfile": "Dockerfile.vscode"
},
"customizations": {
"vscode": {
"settings": {
"terminal.integrated.profiles.linux": {
"bash": {
"path": "/bin/bash",
"args": ["-l"]
}
},
"terminal.integrated.defaultProfile.linux": "bash"
},
"extensions": [
"ms-vscode.cpptools",
"eamodio.gitlens"
]
}
},
// Map the host .ssh folder into the container for a seamless ssh experience
"mounts": [
"source=${localEnv:HOME}${localEnv:USERPROFILE}/.ssh,target=/home/optee/.ssh,type=bind,consistency=cached"
]
}
.vscode/extensions.json 0 → 100644
View file @ a5442c30
{
"recommendations": [
"ms-vscode-remote.remote-containers",
"ms-vscode-remote.remote-wsl",
"ms-vscode-remote.vscode-remote-extensionpack",
"ms-vscode.cpptools-extension-pack",
"ms-vscode.cpptools",
"eamodio.gitlens",
]
}
CHANGELOG.md
View file @ a5442c30
# OP-TEE - version 4.5.0 (2025-01-17)
- Links to the release pages, commits and pull requests merged into this release for:
- OP-TEE/optee_os: [release page][OP_TEE_optee_os_release_4_5_0], [commits][OP_TEE_optee_os_commits_4_5_0] and [pull requests][OP_TEE_optee_os_pr_4_5_0]
- OP-TEE/optee_client: [release page][OP_TEE_optee_client_release_4_5_0], [commits][OP_TEE_optee_client_commits_4_5_0] and [pull requests][OP_TEE_optee_client_pr_4_5_0]
- OP-TEE/optee_test: [release page][OP_TEE_optee_test_release_4_5_0], [commits][OP_TEE_optee_test_commits_4_5_0] and [pull requests][OP_TEE_optee_test_pr_4_5_0]
- OP-TEE/build: [release page][OP_TEE_build_release_4_5_0], [commits][OP_TEE_build_commits_4_5_0] and [pull requests][OP_TEE_build_pr_4_5_0]
- linaro-swg/optee_examples: [release page][linaro_swg_optee_examples_release_4_5_0], [commits][linaro_swg_optee_examples_commits_4_5_0] and [pull requests][linaro_swg_optee_examples_pr_4_5_0]
[OP_TEE_optee_os_release_4_5_0]: https://github.com/OP-TEE/optee_os/releases/tag/4.5.0
[OP_TEE_optee_os_commits_4_5_0]: https://github.com/OP-TEE/optee_os/compare/4.4.0...4.5.0
[OP_TEE_optee_os_pr_4_5_0]: https://github.com/OP-TEE/optee_os/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-10-18..2025-01-17
[OP_TEE_optee_client_release_4_5_0]: https://github.com/OP-TEE/optee_client/releases/tag/4.5.0
[OP_TEE_optee_client_commits_4_5_0]: https://github.com/OP-TEE/optee_client/compare/4.4.0...4.5.0
[OP_TEE_optee_client_pr_4_5_0]: https://github.com/OP-TEE/optee_client/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-10-18..2025-01-17
[OP_TEE_optee_test_release_4_5_0]: https://github.com/OP-TEE/optee_test/releases/tag/4.5.0
[OP_TEE_optee_test_commits_4_5_0]: https://github.com/OP-TEE/optee_test/compare/4.4.0...4.5.0
[OP_TEE_optee_test_pr_4_5_0]: https://github.com/OP-TEE/optee_test/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-10-18..2025-01-17
[OP_TEE_build_release_4_5_0]: https://github.com/OP-TEE/build/releases/tag/4.5.0
[OP_TEE_build_commits_4_5_0]: https://github.com/OP-TEE/build/compare/4.4.0...4.5.0
[OP_TEE_build_pr_4_5_0]: https://github.com/OP-TEE/build/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-10-18..2025-01-17
[linaro_swg_optee_examples_release_4_5_0]: https://github.com/linaro-swg/optee_examples/releases/tag/4.5.0
[linaro_swg_optee_examples_commits_4_5_0]: https://github.com/linaro-swg/optee_examples/compare/4.4.0...4.5.0
[linaro_swg_optee_examples_pr_4_5_0]: https://github.com/linaro-swg/optee_examples/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-10-18..2025-01-17
# OP-TEE - version 4.4.0 (2024-10-18)
- Links to the release pages, commits and pull requests merged into this release for:
- OP-TEE/optee_os: [release page][OP_TEE_optee_os_release_4_4_0], [commits][OP_TEE_optee_os_commits_4_4_0] and [pull requests][OP_TEE_optee_os_pr_4_4_0]
- OP-TEE/optee_client: [release page][OP_TEE_optee_client_release_4_4_0], [commits][OP_TEE_optee_client_commits_4_4_0] and [pull requests][OP_TEE_optee_client_pr_4_4_0]
- OP-TEE/optee_test: [release page][OP_TEE_optee_test_release_4_4_0], [commits][OP_TEE_optee_test_commits_4_4_0] and [pull requests][OP_TEE_optee_test_pr_4_4_0]
- OP-TEE/build: [release page][OP_TEE_build_release_4_4_0], [commits][OP_TEE_build_commits_4_4_0] and [pull requests][OP_TEE_build_pr_4_4_0]
- linaro-swg/optee_examples: [release page][linaro_swg_optee_examples_release_4_4_0], [commits][linaro_swg_optee_examples_commits_4_4_0] and [pull requests][linaro_swg_optee_examples_pr_4_4_0]
[OP_TEE_optee_os_release_4_4_0]: https://github.com/OP-TEE/optee_os/releases/tag/4.4.0
[OP_TEE_optee_os_commits_4_4_0]: https://github.com/OP-TEE/optee_os/compare/4.3.0...4.4.0
[OP_TEE_optee_os_pr_4_4_0]: https://github.com/OP-TEE/optee_os/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-07-12..2024-10-18
[OP_TEE_optee_client_release_4_4_0]: https://github.com/OP-TEE/optee_client/releases/tag/4.4.0
[OP_TEE_optee_client_commits_4_4_0]: https://github.com/OP-TEE/optee_client/compare/4.3.0...4.4.0
[OP_TEE_optee_client_pr_4_4_0]: https://github.com/OP-TEE/optee_client/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-07-12..2024-10-18
[OP_TEE_optee_test_release_4_4_0]: https://github.com/OP-TEE/optee_test/releases/tag/4.4.0
[OP_TEE_optee_test_commits_4_4_0]: https://github.com/OP-TEE/optee_test/compare/4.3.0...4.4.0
[OP_TEE_optee_test_pr_4_4_0]: https://github.com/OP-TEE/optee_test/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-07-12..2024-10-18
[OP_TEE_build_release_4_4_0]: https://github.com/OP-TEE/build/releases/tag/4.4.0
[OP_TEE_build_commits_4_4_0]: https://github.com/OP-TEE/build/compare/4.3.0...4.4.0
[OP_TEE_build_pr_4_4_0]: https://github.com/OP-TEE/build/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-07-12..2024-10-18
[linaro_swg_optee_examples_release_4_4_0]: https://github.com/linaro-swg/optee_examples/releases/tag/4.4.0
[linaro_swg_optee_examples_commits_4_4_0]: https://github.com/linaro-swg/optee_examples/compare/4.3.0...4.4.0
[linaro_swg_optee_examples_pr_4_4_0]: https://github.com/linaro-swg/optee_examples/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-07-12..2024-10-18
# OP-TEE - version 4.3.0 (2024-07-12)
- Links to the release pages, commits and pull requests merged into this release for:
- OP-TEE/optee_os: [release page][OP_TEE_optee_os_release_4_3_0], [commits][OP_TEE_optee_os_commits_4_3_0] and [pull requests][OP_TEE_optee_os_pr_4_3_0]
- OP-TEE/optee_client: [release page][OP_TEE_optee_client_release_4_3_0], [commits][OP_TEE_optee_client_commits_4_3_0] and [pull requests][OP_TEE_optee_client_pr_4_3_0]
- OP-TEE/optee_test: [release page][OP_TEE_optee_test_release_4_3_0], [commits][OP_TEE_optee_test_commits_4_3_0] and [pull requests][OP_TEE_optee_test_pr_4_3_0]
- OP-TEE/build: [release page][OP_TEE_build_release_4_3_0], [commits][OP_TEE_build_commits_4_3_0] and [pull requests][OP_TEE_build_pr_4_3_0]
- linaro-swg/optee_examples: [release page][linaro_swg_optee_examples_release_4_3_0], [commits][linaro_swg_optee_examples_commits_4_3_0] and [pull requests][linaro_swg_optee_examples_pr_4_3_0]
[OP_TEE_optee_os_release_4_3_0]: https://github.com/OP-TEE/optee_os/releases/tag/4.3.0
[OP_TEE_optee_os_commits_4_3_0]: https://github.com/OP-TEE/optee_os/compare/4.2.0...4.3.0
[OP_TEE_optee_os_pr_4_3_0]: https://github.com/OP-TEE/optee_os/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-04-12..2024-07-12
[OP_TEE_optee_client_release_4_3_0]: https://github.com/OP-TEE/optee_client/releases/tag/4.3.0
[OP_TEE_optee_client_commits_4_3_0]: https://github.com/OP-TEE/optee_client/compare/4.2.0...4.3.0
[OP_TEE_optee_client_pr_4_3_0]: https://github.com/OP-TEE/optee_client/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-04-12..2024-07-12
[OP_TEE_optee_test_release_4_3_0]: https://github.com/OP-TEE/optee_test/releases/tag/4.3.0
[OP_TEE_optee_test_commits_4_3_0]: https://github.com/OP-TEE/optee_test/compare/4.2.0...4.3.0
[OP_TEE_optee_test_pr_4_3_0]: https://github.com/OP-TEE/optee_test/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-04-12..2024-07-12
[OP_TEE_build_release_4_3_0]: https://github.com/OP-TEE/build/releases/tag/4.3.0
[OP_TEE_build_commits_4_3_0]: https://github.com/OP-TEE/build/compare/4.2.0...4.3.0
[OP_TEE_build_pr_4_3_0]: https://github.com/OP-TEE/build/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-04-12..2024-07-12
[linaro_swg_optee_examples_release_4_3_0]: https://github.com/linaro-swg/optee_examples/releases/tag/4.3.0
[linaro_swg_optee_examples_commits_4_3_0]: https://github.com/linaro-swg/optee_examples/compare/4.2.0...4.3.0
[linaro_swg_optee_examples_pr_4_3_0]: https://github.com/linaro-swg/optee_examples/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-04-12..2024-07-12
# OP-TEE - version 4.2.0 (2024-04-12)
- Links to the release pages, commits and pull requests merged into this release for:
- OP-TEE/optee_os: [release page][OP_TEE_optee_os_release_4_2_0], [commits][OP_TEE_optee_os_commits_4_2_0] and [pull requests][OP_TEE_optee_os_pr_4_2_0]
- OP-TEE/optee_client: [release page][OP_TEE_optee_client_release_4_2_0], [commits][OP_TEE_optee_client_commits_4_2_0] and [pull requests][OP_TEE_optee_client_pr_4_2_0]
- OP-TEE/optee_test: [release page][OP_TEE_optee_test_release_4_2_0], [commits][OP_TEE_optee_test_commits_4_2_0] and [pull requests][OP_TEE_optee_test_pr_4_2_0]
- OP-TEE/build: [release page][OP_TEE_build_release_4_2_0], [commits][OP_TEE_build_commits_4_2_0] and [pull requests][OP_TEE_build_pr_4_2_0]
- linaro-swg/optee_examples: [release page][linaro_swg_optee_examples_release_4_2_0], [commits][linaro_swg_optee_examples_commits_4_2_0] and [pull requests][linaro_swg_optee_examples_pr_4_2_0]
[OP_TEE_optee_os_release_4_2_0]: https://github.com/OP-TEE/optee_os/releases/tag/4.2.0
[OP_TEE_optee_os_commits_4_2_0]: https://github.com/OP-TEE/optee_os/compare/4.1.0...4.2.0
[OP_TEE_optee_os_pr_4_2_0]: https://github.com/OP-TEE/optee_os/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-01-19..2024-04-12
[OP_TEE_optee_client_release_4_2_0]: https://github.com/OP-TEE/optee_client/releases/tag/4.2.0
[OP_TEE_optee_client_commits_4_2_0]: https://github.com/OP-TEE/optee_client/compare/4.1.0...4.2.0
[OP_TEE_optee_client_pr_4_2_0]: https://github.com/OP-TEE/optee_client/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-01-19..2024-04-12
[OP_TEE_optee_test_release_4_2_0]: https://github.com/OP-TEE/optee_test/releases/tag/4.2.0
[OP_TEE_optee_test_commits_4_2_0]: https://github.com/OP-TEE/optee_test/compare/4.1.0...4.2.0
[OP_TEE_optee_test_pr_4_2_0]: https://github.com/OP-TEE/optee_test/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-01-19..2024-04-12
[OP_TEE_build_release_4_2_0]: https://github.com/OP-TEE/build/releases/tag/4.2.0
[OP_TEE_build_commits_4_2_0]: https://github.com/OP-TEE/build/compare/4.1.0...4.2.0
[OP_TEE_build_pr_4_2_0]: https://github.com/OP-TEE/build/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-01-19..2024-04-12
[linaro_swg_optee_examples_release_4_2_0]: https://github.com/linaro-swg/optee_examples/releases/tag/4.2.0
[linaro_swg_optee_examples_commits_4_2_0]: https://github.com/linaro-swg/optee_examples/compare/4.1.0...4.2.0
[linaro_swg_optee_examples_pr_4_2_0]: https://github.com/linaro-swg/optee_examples/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-01-19..2024-04-12
# OP-TEE - version 4.1.0 (2024-01-19)
- Links to the release pages, commits and pull requests merged into this release for:
- OP-TEE/optee_os: [release page][OP_TEE_optee_os_release_4_1], [commits][OP_TEE_optee_os_commits_4_1] and [pull requests][OP_TEE_optee_os_pr_4_1]
- OP-TEE/optee_client: [release page][OP_TEE_optee_client_release_4_1], [commits][OP_TEE_optee_client_commits_4_1] and [pull requests][OP_TEE_optee_client_pr_4_1]
- OP-TEE/optee_test: [release page][OP_TEE_optee_test_release_4_1], [commits][OP_TEE_optee_test_commits_4_1] and [pull requests][OP_TEE_optee_test_pr_4_1]
- OP-TEE/build: [release page][OP_TEE_build_release_4_1], [commits][OP_TEE_build_commits_4_1] and [pull requests][OP_TEE_build_pr_4_1]
- linaro-swg/optee_examples: [release page][linaro_swg_optee_examples_release_4_1], [commits][linaro_swg_optee_examples_commits_4_1] and [pull requests][linaro_swg_optee_examples_pr_4_1]
[OP_TEE_optee_os_release_4_1]: https://github.com/OP-TEE/optee_os/releases/tag/4.1.0
[OP_TEE_optee_os_commits_4_1]: https://github.com/OP-TEE/optee_os/compare/4.0.0...4.1.0
[OP_TEE_optee_os_pr_4_1]: https://github.com/OP-TEE/optee_os/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-10-20..2024-01-19
[OP_TEE_optee_client_release_4_1]: https://github.com/OP-TEE/optee_client/releases/tag/4.1.0
[OP_TEE_optee_client_commits_4_1]: https://github.com/OP-TEE/optee_client/compare/4.0.0...4.1.0
[OP_TEE_optee_client_pr_4_1]: https://github.com/OP-TEE/optee_client/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-10-20..2024-01-19
[OP_TEE_optee_test_release_4_1]: https://github.com/OP-TEE/optee_test/releases/tag/4.1.0
[OP_TEE_optee_test_commits_4_1]: https://github.com/OP-TEE/optee_test/compare/4.0.0...4.1.0
[OP_TEE_optee_test_pr_4_1]: https://github.com/OP-TEE/optee_test/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-10-20..2024-01-19
[OP_TEE_build_release_4_1]: https://github.com/OP-TEE/build/releases/tag/4.1.0
[OP_TEE_build_commits_4_1]: https://github.com/OP-TEE/build/compare/4.0.0...4.1.0
[OP_TEE_build_pr_4_1]: https://github.com/OP-TEE/build/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-10-20..2024-01-19
[linaro_swg_optee_examples_release_4_1]: https://github.com/linaro-swg/optee_examples/releases/tag/4.1.0
[linaro_swg_optee_examples_commits_4_1]: https://github.com/linaro-swg/optee_examples/compare/4.0.0...4.1.0
[linaro_swg_optee_examples_pr_4_1]: https://github.com/linaro-swg/optee_examples/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-10-20..2024-01-19
# OP-TEE - version 4.0.0 (2023-10-20) # OP-TEE - version 4.0.0 (2023-10-20)
- Links to the release pages, commits and pull requests merged into this release for: - Links to the release pages, commits and pull requests merged into this release for:
...@@ -10,25 +160,25 @@ ...@@ -10,25 +160,25 @@
[OP_TEE_optee_os_release_4_0]: https://github.com/OP-TEE/optee_os/releases/tag/4.0.0 [OP_TEE_optee_os_release_4_0]: https://github.com/OP-TEE/optee_os/releases/tag/4.0.0
[OP_TEE_optee_os_commits_4_0]: https://github.com/OP-TEE/optee_os/compare/3.22.0...4.0.0 [OP_TEE_optee_os_commits_4_0]: https://github.com/OP-TEE/optee_os/compare/3.22.0...4.0.0
[OP_TEE_optee_os_pr_4_0]: https://github.com/OP-TEE/optee_os/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A..2023-10-20 [OP_TEE_optee_os_pr_4_0]: https://github.com/OP-TEE/optee_os/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-07-07..2023-10-20
[OP_TEE_optee_client_release_4_0]: https://github.com/OP-TEE/optee_client/releases/tag/4.0.0 [OP_TEE_optee_client_release_4_0]: https://github.com/OP-TEE/optee_client/releases/tag/4.0.0
[OP_TEE_optee_client_commits_4_0]: https://github.com/OP-TEE/optee_client/compare/3.22.0...4.0.0 [OP_TEE_optee_client_commits_4_0]: https://github.com/OP-TEE/optee_client/compare/3.22.0...4.0.0
[OP_TEE_optee_client_pr_4_0]: https://github.com/OP-TEE/optee_client/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A..2023-10-20 [OP_TEE_optee_client_pr_4_0]: https://github.com/OP-TEE/optee_client/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-07-07..2023-10-20
[OP_TEE_optee_test_release_4_0]: https://github.com/OP-TEE/optee_test/releases/tag/4.0.0 [OP_TEE_optee_test_release_4_0]: https://github.com/OP-TEE/optee_test/releases/tag/4.0.0
[OP_TEE_optee_test_commits_4_0]: https://github.com/OP-TEE/optee_test/compare/3.22.0...4.0.0 [OP_TEE_optee_test_commits_4_0]: https://github.com/OP-TEE/optee_test/compare/3.22.0...4.0.0
[OP_TEE_optee_test_pr_4_0]: https://github.com/OP-TEE/optee_test/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A..2023-10-20 [OP_TEE_optee_test_pr_4_0]: https://github.com/OP-TEE/optee_test/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-07-07..2023-10-20
[OP_TEE_build_release_4_0]: https://github.com/OP-TEE/build/releases/tag/4.0.0 [OP_TEE_build_release_4_0]: https://github.com/OP-TEE/build/releases/tag/4.0.0
[OP_TEE_build_commits_4_0]: https://github.com/OP-TEE/build/compare/3.22.0...4.0.0 [OP_TEE_build_commits_4_0]: https://github.com/OP-TEE/build/compare/3.22.0...4.0.0
[OP_TEE_build_pr_4_0]: https://github.com/OP-TEE/build/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A..2023-10-20 [OP_TEE_build_pr_4_0]: https://github.com/OP-TEE/build/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-07-07..2023-10-20
[linaro_swg_optee_examples_release_4_0]: https://github.com/linaro-swg/optee_examples/releases/tag/4.0.0 [linaro_swg_optee_examples_release_4_0]: https://github.com/linaro-swg/optee_examples/releases/tag/4.0.0
[linaro_swg_optee_examples_commits_4_0]: https://github.com/linaro-swg/optee_examples/compare/3.22.0...4.0.0 [linaro_swg_optee_examples_commits_4_0]: https://github.com/linaro-swg/optee_examples/compare/3.22.0...4.0.0
[linaro_swg_optee_examples_pr_4_0]: https://github.com/linaro-swg/optee_examples/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A..2023-10-20 [linaro_swg_optee_examples_pr_4_0]: https://github.com/linaro-swg/optee_examples/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-07-07..2023-10-20
# OP-TEE - version 3.22 (2023-07-07) # OP-TEE - version 3.22.0 (2023-07-07)
- Links to the release pages, commits and pull requests merged into this release for: - Links to the release pages, commits and pull requests merged into this release for:
- OP-TEE/optee_os: [release page][OP_TEE_optee_os_release_3_22], [commits][OP_TEE_optee_os_commits_3_22] and [pull requests][OP_TEE_optee_os_pr_3_22] - OP-TEE/optee_os: [release page][OP_TEE_optee_os_release_3_22], [commits][OP_TEE_optee_os_commits_3_22] and [pull requests][OP_TEE_optee_os_pr_3_22]
...@@ -38,25 +188,25 @@ ...@@ -38,25 +188,25 @@
- linaro-swg/optee_examples: [release page][linaro_swg_optee_examples_release_3_22], [commits][linaro_swg_optee_examples_commits_3_22] and [pull requests][linaro_swg_optee_examples_pr_3_22] - linaro-swg/optee_examples: [release page][linaro_swg_optee_examples_release_3_22], [commits][linaro_swg_optee_examples_commits_3_22] and [pull requests][linaro_swg_optee_examples_pr_3_22]
[OP_TEE_optee_os_release_3_22]: https://github.com/OP-TEE/optee_os/releases/tag/3.22 [OP_TEE_optee_os_release_3_22]: https://github.com/OP-TEE/optee_os/releases/tag/3.22.0
[OP_TEE_optee_os_commits_3_22]: https://github.com/OP-TEE/optee_os/compare/3.21...3.22 [OP_TEE_optee_os_commits_3_22]: https://github.com/OP-TEE/optee_os/compare/3.21.0...3.22.0
[OP_TEE_optee_os_pr_3_22]: https://github.com/OP-TEE/optee_os/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A..2023-07-07 [OP_TEE_optee_os_pr_3_22]: https://github.com/OP-TEE/optee_os/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-04-14..2023-07-07
[OP_TEE_optee_client_release_3_22]: https://github.com/OP-TEE/optee_client/releases/tag/3.22 [OP_TEE_optee_client_release_3_22]: https://github.com/OP-TEE/optee_client/releases/tag/3.22.0
[OP_TEE_optee_client_commits_3_22]: https://github.com/OP-TEE/optee_client/compare/3.21...3.22 [OP_TEE_optee_client_commits_3_22]: https://github.com/OP-TEE/optee_client/compare/3.21.0...3.22.0
[OP_TEE_optee_client_pr_3_22]: https://github.com/OP-TEE/optee_client/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A..2023-07-07 [OP_TEE_optee_client_pr_3_22]: https://github.com/OP-TEE/optee_client/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-04-14..2023-07-07
[OP_TEE_optee_test_release_3_22]: https://github.com/OP-TEE/optee_test/releases/tag/3.22 [OP_TEE_optee_test_release_3_22]: https://github.com/OP-TEE/optee_test/releases/tag/3.22.0
[OP_TEE_optee_test_commits_3_22]: https://github.com/OP-TEE/optee_test/compare/3.21...3.22 [OP_TEE_optee_test_commits_3_22]: https://github.com/OP-TEE/optee_test/compare/3.21.0...3.22.0
[OP_TEE_optee_test_pr_3_22]: https://github.com/OP-TEE/optee_test/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A..2023-07-07 [OP_TEE_optee_test_pr_3_22]: https://github.com/OP-TEE/optee_test/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-04-14..2023-07-07
[OP_TEE_build_release_3_22]: https://github.com/OP-TEE/build/releases/tag/3.22 [OP_TEE_build_release_3_22]: https://github.com/OP-TEE/build/releases/tag/3.22.0
[OP_TEE_build_commits_3_22]: https://github.com/OP-TEE/build/compare/3.21...3.22 [OP_TEE_build_commits_3_22]: https://github.com/OP-TEE/build/compare/3.21.0...3.22.0
[OP_TEE_build_pr_3_22]: https://github.com/OP-TEE/build/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A..2023-07-07 [OP_TEE_build_pr_3_22]: https://github.com/OP-TEE/build/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-04-14..2023-07-07
[linaro_swg_optee_examples_release_3_22]: https://github.com/linaro-swg/optee_examples/releases/tag/3.22 [linaro_swg_optee_examples_release_3_22]: https://github.com/linaro-swg/optee_examples/releases/tag/3.22.0
[linaro_swg_optee_examples_commits_3_22]: https://github.com/linaro-swg/optee_examples/compare/3.21...3.22 [linaro_swg_optee_examples_commits_3_22]: https://github.com/linaro-swg/optee_examples/compare/3.21.0...3.22.0
[linaro_swg_optee_examples_pr_3_22]: https://github.com/linaro-swg/optee_examples/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A..2023-07-07 [linaro_swg_optee_examples_pr_3_22]: https://github.com/linaro-swg/optee_examples/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2023-04-14..2023-07-07
# OP-TEE - version 3.21.0 (2023-04-14) # OP-TEE - version 3.21.0 (2023-04-14)
......
MAINTAINERS
View file @ a5442c30
...@@ -32,6 +32,11 @@ basis (R:). ...@@ -32,6 +32,11 @@ basis (R:).
---------- ----------
AOSP build
R: Tadd Kao <tadd.kao@mediatek.com> [@taddk]
S: Maintained
F: mk/aosp_optee.mk
ARM Foundation FVP ARM Foundation FVP
R: Jens Wiklander <jens.wiklander@linaro.org> [@jenswi-linaro] R: Jens Wiklander <jens.wiklander@linaro.org> [@jenswi-linaro]
S: Maintained S: Maintained
...@@ -57,6 +62,12 @@ R: Amit Singh Tomar <amittomer25@gmail.com> [@Amit-Radur] ...@@ -57,6 +62,12 @@ R: Amit Singh Tomar <amittomer25@gmail.com> [@Amit-Radur]
S: Maintained S: Maintained
F: core/arch/arm/plat-sunxi/ F: core/arch/arm/plat-sunxi/
AMD Versal Gen 2
R: Michal Simek <michal.simek@amd.com> [@michalsimek]
R: Akshay Belsare <akshay.belsare@amd.com> [@Akshay-Belsare]
S: Maintained
F: core/arch/arm/plat-versal2/
AmLogic AXG (A113D) AmLogic AXG (A113D)
R: Carlo Caione <ccaione@baylibre.com> [@carlocaione] R: Carlo Caione <ccaione@baylibre.com> [@carlocaione]
S: Maintained S: Maintained
...@@ -175,7 +186,7 @@ F: core/drivers/ls_dspi.c ...@@ -175,7 +186,7 @@ F: core/drivers/ls_dspi.c
NXP (Freescale) i.MX family NXP (Freescale) i.MX family
R: Peng Fan <peng.fan@nxp.com> [@MrVan] R: Peng Fan <peng.fan@nxp.com> [@MrVan]
R: Silvano Di Ninno <silvano.dininno@nxp.com> [@sdininno] R: Silvano Di Ninno <silvano.dininno@nxp.com> [@sdininno]
R: Clement Faure <clement.faure@nxp.com> [@clementfaure] R: Sahil Malhotra <sahil.malhotra@nxp.com> [@sahilnxp]
S: Maintained S: Maintained
F: core/arch/arm/plat-imx/ F: core/arch/arm/plat-imx/
F: core/arch/arm/plat-imx/registers F: core/arch/arm/plat-imx/registers
...@@ -199,7 +210,7 @@ F: core/drivers/clk/ ...@@ -199,7 +210,7 @@ F: core/drivers/clk/
Crypto driver interface Crypto driver interface
R: Cedric Neveux <cedric.neveux@nxp.com> [@cneveux] R: Cedric Neveux <cedric.neveux@nxp.com> [@cneveux]
R: Silvano Di Ninno <silvano.dininno@nxp.com> [@sdininno] R: Silvano Di Ninno <silvano.dininno@nxp.com> [@sdininno]
R: Clement Faure <clement.faure@nxp.com> [@clementfaure] R: Sahil Malhotra <sahil.malhotra@nxp.com> [@sahilnxp]
S: Maintained S: Maintained
F: core/drivers/crypto/ F: core/drivers/crypto/
...@@ -267,14 +278,25 @@ R: Etienne Carriere <etienne.carriere@foss.st.com> [@etienne-lms] ...@@ -267,14 +278,25 @@ R: Etienne Carriere <etienne.carriere@foss.st.com> [@etienne-lms]
S: Maintained S: Maintained
F: core/arch/arm/plat-stm/ F: core/arch/arm/plat-stm/
STMicroelectronics drivers
R: Etienne Carriere <etienne.carriere@foss.st.com> [@etienne-lms]
R: Gatien Chevallier <gatien.chevallier@foss.st.com> [@GseoC]
S: Maintained
F: core/drivers/stm32_*
STMicroelectronics stm32mp1 STMicroelectronics stm32mp1
R: Etienne Carriere <etienne.carriere@foss.st.com> [@etienne-lms] R: Etienne Carriere <etienne.carriere@foss.st.com> [@etienne-lms]
S: Maintained S: Maintained
F: core/arch/arm/plat-stm32mp1/ F: core/arch/arm/plat-stm32mp1/
F: core/drivers/stm32_*
F: core/drivers/stm32mp15_huk.c F: core/drivers/stm32mp15_huk.c
F: core/drivers/stpmic1.c F: core/drivers/stpmic1.c
STMicroelectronics stm32mp2
R: Etienne Carriere <etienne.carriere@foss.st.com> [@etienne-lms]
R: Gatien Chevallier <gatien.chevallier@foss.st.com> [@GseoC]
S: Maintained
F: core/arch/arm/plat-stm32mp2/*
Texas Instruments AM43xx, AM57xx, DRA7xx, AM65x, J721E, J784S4, AM64x, AM62x Texas Instruments AM43xx, AM57xx, DRA7xx, AM65x, J721E, J784S4, AM64x, AM62x
R: Andrew Davis <afd@ti.com> [@glneo] R: Andrew Davis <afd@ti.com> [@glneo]
S: Maintained S: Maintained
...@@ -308,6 +330,13 @@ R: Neal Liu <neal_liu@aspeedtech.com> [@Neal-liu] ...@@ -308,6 +330,13 @@ R: Neal Liu <neal_liu@aspeedtech.com> [@Neal-liu]
S: Maintained S: Maintained
F: core/arch/arm/plat-aspeed/ F: core/arch/arm/plat-aspeed/
Telechips TCC805x
R: Sungmin Han <sungminhan@telechips.com> [@meeneemaru]
R: GY Hwang <gy.hwang@telechips.com> [@hwang-telechips]
S: Maintained
F: core/arch/arm/plat-telechips/
F: core/drivers/openedges_omc.c
RISC-V RISC-V
R: Marouene Boubakri <marouene.boubakri@nxp.com> [@maroueneboubakri] R: Marouene Boubakri <marouene.boubakri@nxp.com> [@maroueneboubakri]
S: Maintained S: Maintained
......
Makefile
View file @ a5442c30
...@@ -109,6 +109,7 @@ clean: ...@@ -109,6 +109,7 @@ clean:
${q}dirs="$(call cleandirs-for-rmdir)"; if [ "$$dirs" ]; then $(RMDIR) $$dirs; fi ${q}dirs="$(call cleandirs-for-rmdir)"; if [ "$$dirs" ]; then $(RMDIR) $$dirs; fi
@if [ "$(out-dir)" != "$(O)" ]; then $(cmd-echo-silent) ' CLEAN $(O)'; fi @if [ "$(out-dir)" != "$(O)" ]; then $(cmd-echo-silent) ' CLEAN $(O)'; fi
${q}if [ -d "$(O)" ]; then $(RMDIR) $(O); fi ${q}if [ -d "$(O)" ]; then $(RMDIR) $(O); fi
${q}rm -f compile_commands.json
.PHONY: cscope .PHONY: cscope
cscope: cscope:
......
core/arch/arm/arm.mk
View file @ a5442c30
...@@ -21,6 +21,9 @@ $(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) ...@@ -21,6 +21,9 @@ $(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead)
endif endif
CFG_LPAE_ADDR_SPACE_BITS ?= 32 CFG_LPAE_ADDR_SPACE_BITS ?= 32
ifeq ($(CFG_ARM32_core),y)
$(call force,CFG_LPAE_ADDR_SPACE_BITS,32)
endif
CFG_MMAP_REGIONS ?= 13 CFG_MMAP_REGIONS ?= 13
CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10)
...@@ -129,6 +132,9 @@ ifeq ($(CFG_CORE_FFA),y) ...@@ -129,6 +132,9 @@ ifeq ($(CFG_CORE_FFA),y)
ifneq ($(CFG_DT),y) ifneq ($(CFG_DT),y)
$(error CFG_CORE_FFA depends on CFG_DT) $(error CFG_CORE_FFA depends on CFG_DT)
endif endif
ifneq ($(CFG_ARM64_core),y)
$(error CFG_CORE_FFA depends on CFG_ARM64_core)
endif
endif endif
ifeq ($(CFG_CORE_PHYS_RELOCATABLE)-$(CFG_WITH_PAGER),y-y) ifeq ($(CFG_CORE_PHYS_RELOCATABLE)-$(CFG_WITH_PAGER),y-y)
...@@ -179,7 +185,8 @@ CFG_SM_NO_CYCLE_COUNTING ?= y ...@@ -179,7 +185,8 @@ CFG_SM_NO_CYCLE_COUNTING ?= y
# CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free # CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free
# interrupt. Setting it to a non-zero number enables support for using an # interrupt. Setting it to a non-zero number enables support for using an
# Arm-GIC to notify normal world. This config variable should use a value # Arm-GIC to notify normal world. This config variable should use a value
# larger the 32 to make it of the type SPI. # larger or equal to 24 to make it of the type SPI or PPI (secure PPI
# only).
# Note that asynchronous notifactions must be enabled with # Note that asynchronous notifactions must be enabled with
# CFG_CORE_ASYNC_NOTIF=y for this variable to be used. # CFG_CORE_ASYNC_NOTIF=y for this variable to be used.
CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0 CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0
......
core/arch/arm/cpu/cortex-armv9.mk 0 → 100644
View file @ a5442c30
$(call force,CFG_HWSUPP_MEM_PERM_WXN,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
$(call force,CFG_ENABLE_SCTLR_RR,n)
$(call force,CFG_ENABLE_SCTLR_Z,n)
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-cxxflags += -mcpu=$(arm32-platform-cpuarch)
arm64-platform-cflags += -mcpu=$(arm64-platform-cpuarch)
arm64-platform-aflags += -mcpu=$(arm64-platform-cpuarch)
arm64-platform-cxxflags += -mcpu=$(arm64-platform-cpuarch)
platform-flavor-armv9 := 1
core/arch/arm/cpu/neoverse-v2.mk 0 → 100644
View file @ a5442c30
arm32-platform-cpuarch := neoverse-v2
arm64-platform-cpuarch := neoverse-v2
include core/arch/arm/cpu/cortex-armv9.mk
core/arch/arm/crypto/aes_modes_armv8a_ce_a64.S
View file @ a5442c30
...@@ -507,7 +507,6 @@ FUNC ce_aes_xts_encrypt , : ...@@ -507,7 +507,6 @@ FUNC ce_aes_xts_encrypt , :
b .LxtsencNx b .LxtsencNx
.LxtsencloopNx: .LxtsencloopNx:
ldr q7, .Lxts_mul_x
next_tweak v4, v4, v7, v8 next_tweak v4, v4, v7, v8
.LxtsencNx: .LxtsencNx:
#if INTERLEAVE >= 2 #if INTERLEAVE >= 2
...@@ -544,6 +543,7 @@ FUNC ce_aes_xts_encrypt , : ...@@ -544,6 +543,7 @@ FUNC ce_aes_xts_encrypt , :
eor v2.16b, v2.16b, v6.16b eor v2.16b, v2.16b, v6.16b
st1 {v0.16b-v3.16b}, [x0], #64 st1 {v0.16b-v3.16b}, [x0], #64
mov v4.16b, v7.16b mov v4.16b, v7.16b
ldr q7, .Lxts_mul_x
cbz w4, .Lxtsencout cbz w4, .Lxtsencout
b .LxtsencloopNx b .LxtsencloopNx
#endif #endif
...@@ -588,7 +588,6 @@ FUNC ce_aes_xts_decrypt , : ...@@ -588,7 +588,6 @@ FUNC ce_aes_xts_decrypt , :
b .LxtsdecNx b .LxtsdecNx
.LxtsdecloopNx: .LxtsdecloopNx:
ldr q7, .Lxts_mul_x
next_tweak v4, v4, v7, v8 next_tweak v4, v4, v7, v8
.LxtsdecNx: .LxtsdecNx:
#if INTERLEAVE >= 2 #if INTERLEAVE >= 2
...@@ -625,6 +624,7 @@ FUNC ce_aes_xts_decrypt , : ...@@ -625,6 +624,7 @@ FUNC ce_aes_xts_decrypt , :
eor v2.16b, v2.16b, v6.16b eor v2.16b, v2.16b, v6.16b
st1 {v0.16b-v3.16b}, [x0], #64 st1 {v0.16b-v3.16b}, [x0], #64
mov v4.16b, v7.16b mov v4.16b, v7.16b
ldr q7, .Lxts_mul_x
cbz w4, .Lxtsdecout cbz w4, .Lxtsdecout
b .LxtsdecloopNx b .LxtsdecloopNx
#endif #endif
......
core/arch/arm/crypto/ghash-ce-core_a64.S
View file @ a5442c30
/* SPDX-License-Identifier: BSD-2-Clause */ /* SPDX-License-Identifier: BSD-2-Clause */
/* /*
* Copyright (c) 2020 Linaro Limited * Copyright (c) 2020, 2024 Linaro Limited
* Copyright (C) 2014 - 2017 Linaro Ltd. <ard.biesheuvel@linaro.org> * Copyright (C) 2014 - 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
* *
* Accelerated GHASH implementation with ARMv8 PMULL instructions. * Accelerated GHASH implementation with ARMv8 PMULL instructions.
...@@ -11,11 +11,10 @@ ...@@ -11,11 +11,10 @@
#define CPU_LE(x...) x #define CPU_LE(x...) x
/* /*
* If the lower half of CTR is initialized with zeroes or a low value we * Only increase the lowest quarter, that is, 32-bits of the counter. If
* can expect that the upper half will remain unchanged. As an optimization * it wraps it must not propagate into the upper bits.
* make the code to increase the upper half optional.
*/ */
#define INC_HALF_CTR 0 #define INC_QUART_CTR 1
SHASH .req v0 SHASH .req v0
SHASH2 .req v1 SHASH2 .req v1
...@@ -412,7 +411,7 @@ END_FUNC pmull_ghash_update_p8 ...@@ -412,7 +411,7 @@ END_FUNC pmull_ghash_update_p8
ld1 {SHASH.2d}, [x4], #16 ld1 {SHASH.2d}, [x4], #16
ld1 {HH.2d}, [x4] ld1 {HH.2d}, [x4]
ld1 {XL.2d}, [x1] ld1 {XL.2d}, [x1]
#if INC_HALF_CTR #if INC_QUART_CTR
ldr x8, [x5, #8] // load lower counter ldr x8, [x5, #8] // load lower counter
#else #else
ldp x9, x8, [x5] // load counter ldp x9, x8, [x5] // load counter
...@@ -422,7 +421,7 @@ END_FUNC pmull_ghash_update_p8 ...@@ -422,7 +421,7 @@ END_FUNC pmull_ghash_update_p8
trn1 SHASH2.2d, SHASH.2d, HH.2d trn1 SHASH2.2d, SHASH.2d, HH.2d
trn2 T1.2d, SHASH.2d, HH.2d trn2 T1.2d, SHASH.2d, HH.2d
CPU_LE( rev x8, x8 ) CPU_LE( rev x8, x8 )
#if !INC_HALF_CTR #if !INC_QUART_CTR
CPU_LE( rev x9, x9 ) CPU_LE( rev x9, x9 )
#endif #endif
shl MASK.2d, MASK.2d, #57 shl MASK.2d, MASK.2d, #57
...@@ -437,10 +436,13 @@ CPU_LE( rev x9, x9 ) ...@@ -437,10 +436,13 @@ CPU_LE( rev x9, x9 )
0: ld1 {INP0.16b-INP1.16b}, [x3], #32 0: ld1 {INP0.16b-INP1.16b}, [x3], #32
#if INC_HALF_CTR #if INC_QUART_CTR
lsr x12, x8, #32 // Save the upper 32 bits
rev x9, x8 rev x9, x8
add x11, x8, #1 add w11, w8, #1
add x8, x8, #2 add w8, w8, #2
add x11, x11, x12, lsl #32 // Restore the upper 32 bits
add x8, x8, x12, lsl #32
#endif #endif
.if \enc == 1 .if \enc == 1
...@@ -450,7 +452,7 @@ CPU_LE( rev x9, x9 ) ...@@ -450,7 +452,7 @@ CPU_LE( rev x9, x9 )
sub w0, w0, #2 sub w0, w0, #2
#if INC_HALF_CTR #if INC_QUART_CTR
ld1 {KS0.8b}, [x5] // load upper counter ld1 {KS0.8b}, [x5] // load upper counter
rev x11, x11 rev x11, x11
mov KS1.8b, KS0.8b mov KS1.8b, KS0.8b
...@@ -563,11 +565,11 @@ CPU_LE( rev x9, x9 ) ...@@ -563,11 +565,11 @@ CPU_LE( rev x9, x9 )
cbnz w0, 0b cbnz w0, 0b
CPU_LE( rev x8, x8 ) CPU_LE( rev x8, x8 )
#if !INC_HALF_CTR #if !INC_QUART_CTR
CPU_LE( rev x9, x9 ) CPU_LE( rev x9, x9 )
#endif #endif
st1 {XL.2d}, [x1] st1 {XL.2d}, [x1]
#if INC_HALF_CTR #if INC_QUART_CTR
str x8, [x5, #8] // store lower counter str x8, [x5, #8] // store lower counter
#else #else
stp x9, x8, [x5] // store counter stp x9, x8, [x5] // store counter
......
core/arch/arm/crypto/sha3_armv8a_ce_a64.S
View file @ a5442c30
...@@ -114,9 +114,8 @@ FUNC sha3_ce_transform , : ...@@ -114,9 +114,8 @@ FUNC sha3_ce_transform , :
b 4f b 4f
/* SHA3-224: digest size 28 bytes, block size 144 bytes */ /* SHA3-224: digest size 28 bytes, block size 144 bytes */
2: ld1 {v25.8b-v26.8b}, [x1], #16 2: ld1 {v29.8b}, [x1], #8
eor v17.8b, v17.8b, v25.8b eor v17.8b, v17.8b, v29.8b
eor v18.8b, v18.8b, v26.8b
b 4f b 4f
/* SHA3-512: digest size 64 bytes , block size 72 bytes */ /* SHA3-512: digest size 64 bytes , block size 72 bytes */
......
core/arch/arm/crypto/sm4_armv8a_ce_a64.S
View file @ a5442c30
...@@ -1028,3 +1028,5 @@ FUNC ce_sm4_xts_decrypt , : ...@@ -1028,3 +1028,5 @@ FUNC ce_sm4_xts_decrypt , :
frame_pop frame_pop
ret ret
END_FUNC ce_sm4_xts_decrypt END_FUNC ce_sm4_xts_decrypt
BTI(emit_aarch64_feature_1_and GNU_PROPERTY_AARCH64_FEATURE_1_BTI)
core/arch/arm/dts/at91-sama7g54_ek.dts 0 → 100644
View file @ a5442c30
// SPDX-License-Identifier: BSD-2-Clause
/*
* at91-sama7g54_ek.dts - Device Tree file for SAMA7G54-EK board
*
* Copyright (c) 2017, Microchip Technology Inc.
* 2016 Nicolas Ferre <nicolas.ferre@atmel.com>
* 2017 Cristian Birsan <cristian.birsan@microchip.com>
* 2017 Claudiu Beznea <claudiu.beznea@microchip.com>
*/
/dts-v1/;
#include "sama7g5-pinfunc.h"
#include "sama7g5.dtsi"
#include <dt-bindings/mfd/atmel-flexcom.h>
/ {
model = "Microchip SAMA7G5-EK";
compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7";
aliases {
serial0 = &uart3;
serial1 = &uart4;
serial2 = &uart7;
serial3 = &uart0;
i2c0 = &i2c1;
i2c1 = &i2c8;
i2c2 = &i2c9;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay"; /* Conflict with pwm. */
red_led {
label = "red";
gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
};
green_led {
label = "green";
gpios = <&pioA PIN_PA13 GPIO_ACTIVE_HIGH>;
};
blue_led {
label = "blue";
gpios = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
/* 512 M */
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x20000000>;
};
sound: sound {
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&pmc PMC_TYPE_CORE PMC_AUDIOPMCPLL>;
assigned-clock-rates = <196608000>;
compatible = "microchip,asrc-card";
microchip,model = "mchp-asrc-card @ sama7g5 EK";
status = "disabled";
microchip,audio-asrc = <&asrc 0>, <&asrc 1>, <&asrc 2>, <&asrc 3>;
microchip,dai-link@0 {
reg = <0>;
microchip,convert-channels = <2>;
microchip,convert-rate = <48000>;
cpu {
sound-dai = <&spdiftx>;
};
codec {
sound-dai = <&spdif_out>;
};
};
microchip,dai-link@1 {
reg = <1>;
microchip,convert-channels = <2>;
microchip,convert-rate = <48000>;
cpu {
sound-dai = <&spdifrx>;
};
codec {
sound-dai = <&spdif_in>;
};
};
};
spdif_in: spdif-in {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dir";
};
spdif_out: spdif-out {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
};
};
&asrc {
status = "okay";
};
&adc {
vddana-supply = <&vddout25>;
vref-supply = <&vddout25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>;
status = "disabled";
};
&can0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_default>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vddcpu>;
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <133000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
m25p,fast-read;
at91bootstrap@0 {
label = "ospi: at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "ospi: bootloader";
reg = <0x40000 0xc0000>;
};
bootloaderenvred@100000 {
label = "ospi: bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenv@140000 {
label = "ospi: bootloader env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "ospi: device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "ospi: kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "ospi: rootfs";
reg = <0x800000 0x7800000>;
};
};
};
&dma0 {
status = "okay";
};
&dma1 {
status = "okay";
};
&dma2 {
status = "okay";
};
&flx0 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "disabled";
uart0: serial@200 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
status = "disabled";
};
};
&flx1 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c1: i2c@600 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "disable";
secure-status = "okay";
pac1934@10 {
compatible = "microchip,pac1934";
reg = <0x10>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
channel@1 {
reg = <0x1>;
shunt-resistor-micro-ohms = <10000>;
label = "VDD3V3";
};
channel@2 {
reg = <0x2>;
shunt-resistor-micro-ohms = <10000>;
label = "VDDIODDR";
};
channel@3 {
reg = <0x3>;
shunt-resistor-micro-ohms = <10000>;
label = "VDDCORE";
};
channel@4 {
reg = <0x4>;
shunt-resistor-micro-ohms = <10000>;
label = "VDDCPU";
};
};
mcp16502@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
status = "okay";
regulators {
vdd_3v3: VDD_IO {
regulator-name = "VDD_IO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vddioddr: VDD_DDR {
regulator-name = "VDD_DDR";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1350000>;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1350000>;
regulator-mode = <4>;
};
};
vddcore: VDD_CORE {
regulator-name = "VDD_CORE";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-voltage = <1150000>;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vddcpu: VDD_OTHER {
regulator-name = "VDD_OTHER";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-ramp-delay = <3125>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-voltage = <1050000>;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-state-standby {
regulator-suspend-voltage = <1800000>;
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
};
vldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3700000>;
regulator-state-standby {
regulator-suspend-voltage = <1800000>;
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
};
&flx3 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart3: serial@200 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
status = "okay";
};
};
&flx4 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart4: serial@200 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
status = "okay";
};
};
&flx7 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart7: serial@200 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx7_default>;
status = "okay";
};
};
&flx8 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c8: i2c@600 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
eeprom0: eeprom0@52 {
compatible = "atmel,24mac02e4";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x52>;
pagesize = <16>;
size = <256>;
status = "okay";
eeprom0_eui48: eui48@fa {
reg = <0xfa 0x6>;
};
};
eeprom1: eeprom1@53 {
compatible = "atmel,24mac02e4";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x53>;
pagesize = <16>;
size = <256>;
status = "okay";
eeprom1_eui48: eui48@fa {
reg = <0xfa 0x6>;
};
};
};
};
&flx9 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c9: i2c@600 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
};
};
&flx11 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
status = "okay";
spi11: spi@400 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>;
status = "okay";
};
};
&gmac0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac0_default
&pinctrl_gmac0_mdio_default
&pinctrl_gmac0_txck_default
&pinctrl_gmac0_phy_irq>;
phy-mode = "rgmii-id";
status = "okay";
nvmem-cells = <&eeprom0_eui48>;
nvmem-cell-names = "mac-address";
ethernet-phy@7 {
reg = <0x7>;
interrupt-parent = <&pioA>;
interrupts = <PIN_PA31 IRQ_TYPE_LEVEL_LOW>;
};
};
&gmac1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac1_default
&pinctrl_gmac1_mdio_default
&pinctrl_gmac1_phy_irq>;
phy-mode = "rmii";
status = "disabled"; /* Conflict with pdmc0. */
nvmem-cells = <&eeprom1_eui48>;
nvmem-cell-names = "mac-address";
ethernet-phy@0 {
reg = <0x0>;
interrupt-parent = <&pioA>;
interrupts = <PIN_PA21 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2s0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s0_default>;
};
&pdmc0 {
#sound-dai-cells = <0>;
status = "disabled"; /* Conflict with gmac1. */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdmc0_default>;
};
&pioA {
pinctrl_can0_default: can0_default {
pinmux = <PIN_PD12__CANTX0>,
<PIN_PD13__CANRX0 >;
bias-disable;
};
pinctrl_can1_default: can1_default {
pinmux = <PIN_PD14__CANTX1>,
<PIN_PD15__CANRX1 >;
bias-disable;
};
pinctrl_flx0_default: flx0_default {
pinmux = <PIN_PE3__FLEXCOM0_IO0>,
<PIN_PE4__FLEXCOM0_IO1>,
<PIN_PE6__FLEXCOM0_IO3>,
<PIN_PE7__FLEXCOM0_IO4>;
bias-disable;
};
pinctrl_flx3_default: flx3_default {
pinmux = <PIN_PD16__FLEXCOM3_IO0>,
<PIN_PD17__FLEXCOM3_IO1>;
bias-pull-up;
};
pinctrl_flx4_default: flx4_default {
pinmux = <PIN_PD18__FLEXCOM4_IO0>,
<PIN_PD19__FLEXCOM4_IO1>;
bias-disable;
};
pinctrl_flx7_default: flx7_default {
pinmux = <PIN_PC23__FLEXCOM7_IO0>,
<PIN_PC24__FLEXCOM7_IO1>;
bias-disable;
};
pinctrl_gmac0_default: gmac0_default {
pinmux = <PIN_PA16__G0_TX0>,
<PIN_PA17__G0_TX1>,
<PIN_PA26__G0_TX2>,
<PIN_PA27__G0_TX3>,
<PIN_PA19__G0_RX0>,
<PIN_PA20__G0_RX1>,
<PIN_PA28__G0_RX2>,
<PIN_PA29__G0_RX3>,
<PIN_PA15__G0_TXEN>,
<PIN_PA30__G0_RXCK>,
<PIN_PA18__G0_RXDV>,
<PIN_PA25__G0_125CK>;
slew-rate = <0>;
bias-disable;
};
pinctrl_gmac0_mdio_default: gmac0_mdio_default {
pinmux = <PIN_PA22__G0_MDC>,
<PIN_PA23__G0_MDIO>;
bias-disable;
};
pinctrl_gmac0_txck_default: gmac0_txck_default {
pinmux = <PIN_PA24__G0_TXCK>;
slew-rate = <0>;
bias-pull-up;
};
pinctrl_gmac0_phy_irq: gmac0_phy_irq {
pinmux = <PIN_PA31__GPIO>;
bias-disable;
};
pinctrl_gmac1_default: gmac1_default {
pinmux = <PIN_PD30__G1_TXCK>,
<PIN_PD22__G1_TX0>,
<PIN_PD23__G1_TX1>,
<PIN_PD21__G1_TXEN>,
<PIN_PD25__G1_RX0>,
<PIN_PD26__G1_RX1>,
<PIN_PD27__G1_RXER>,
<PIN_PD24__G1_RXDV>;
slew-rate = <0>;
bias-disable;
};
pinctrl_gmac1_mdio_default: gmac1_mdio_default {
pinmux = <PIN_PD28__G1_MDC>,
<PIN_PD29__G1_MDIO>;
bias-disable;
};
pinctrl_gmac1_phy_irq: gmac1_phy_irq {
pinmux = <PIN_PA21__GPIO>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PC9__FLEXCOM1_IO0>,
<PIN_PC10__FLEXCOM1_IO1>;
bias-disable;
};
pinctrl_i2c8_default: i2c8_default {
pinmux = <PIN_PC14__FLEXCOM8_IO0>,
<PIN_PC13__FLEXCOM8_IO1>;
bias-disable;
};
pinctrl_i2c9_default: i2c9_default {
pinmux = <PIN_PC18__FLEXCOM9_IO0>,
<PIN_PC19__FLEXCOM9_IO1>;
bias-disable;
};
pinctrl_i2s0_default: i2s0_default {
pinmux = <PIN_PB23__I2SMCC0_CK>,
<PIN_PB24__I2SMCC0_WS>,
<PIN_PB25__I2SMCC0_DOUT1>,
<PIN_PB26__I2SMCC0_DOUT0>,
<PIN_PB27__I2SMCC0_MCK>;
bias-disable;
};
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PA12__GPIO>;
bias-pull-up;
};
pinctrl_led_gpio_default: led_gpio_default {
pinmux = <PIN_PA13__GPIO>,
<PIN_PB8__GPIO>,
<PIN_PD20__GPIO>;
bias-pull-up;
};
pinctrl_mikrobus1_an_default: mikrobus1_an_default {
pinmux = <PIN_PD0__GPIO>;
bias-disable;
};
pinctrl_mikrobus2_an_default: mikrobus2_an_default {
pinmux = <PIN_PD1__GPIO>;
bias-disable;
};
pinctrl_mikrobus1_pwm2_default: mikrobus1_pwm2_default {
pinmux = <PIN_PA13__PWMH2>;
bias-disable;
};
pinctrl_mikrobus2_pwm3_default: mikrobus2_pwm3_default {
pinmux = <PIN_PD20__PWMH3>;
bias-disable;
};
pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs {
pinmux = <PIN_PB6__FLEXCOM11_IO3>;
bias-disable;
};
pinctrl_mikrobus1_spi: mikrobus1_spi {
pinmux = <PIN_PB3__FLEXCOM11_IO0>,
<PIN_PB4__FLEXCOM11_IO1>,
<PIN_PB5__FLEXCOM11_IO2>;
bias-disable;
};
pinctrl_pdmc0_default: pdmc0_default {
pinmux = <PIN_PD23__PDMC0_DS0>,
<PIN_PD24__PDMC0_DS1>,
<PIN_PD22__PDMC0_CLK>;
bias_disable;
};
pinctrl_qspi: qspi {
pinmux = <PIN_PB12__QSPI0_IO0>,
<PIN_PB11__QSPI0_IO1>,
<PIN_PB10__QSPI0_IO2>,
<PIN_PB9__QSPI0_IO3>,
<PIN_PB16__QSPI0_IO4>,
<PIN_PB17__QSPI0_IO5>,
<PIN_PB18__QSPI0_IO6>,
<PIN_PB19__QSPI0_IO7>,
<PIN_PB13__QSPI0_CS>,
<PIN_PB14__QSPI0_SCK>,
<PIN_PB15__QSPI0_SCKN>,
<PIN_PB20__QSPI0_DQS>,
<PIN_PB21__QSPI0_INT>;
bias-disable;
slew-rate = <0>;
};
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_data {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA3__SDMMC0_DAT0>,
<PIN_PA4__SDMMC0_DAT1>,
<PIN_PA5__SDMMC0_DAT2>,
<PIN_PA6__SDMMC0_DAT3>,
<PIN_PA7__SDMMC0_DAT4>,
<PIN_PA8__SDMMC0_DAT5>,
<PIN_PA9__SDMMC0_DAT6>,
<PIN_PA10__SDMMC0_DAT7>;
slew-rate = <0>;
bias-pull-up;
};
ck_cd_rstn_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA2__SDMMC0_RSTN>,
<PIN_PA11__SDMMC0_DS>;
slew-rate = <0>;
bias-pull-up;
};
};
pinctrl_sdmmc1_default: sdmmc1_default {
cmd_data {
pinmux = <PIN_PB29__SDMMC1_CMD>,
<PIN_PB31__SDMMC1_DAT0>,
<PIN_PC0__SDMMC1_DAT1>,
<PIN_PC1__SDMMC1_DAT2>,
<PIN_PC2__SDMMC1_DAT3>;
slew-rate = <0>;
bias-pull-up;
};
ck_cd_rstn_vddsel {
pinmux = <PIN_PB30__SDMMC1_CK>,
<PIN_PB28__SDMMC1_RSTN>,
<PIN_PC5__SDMMC1_1V8SEL>,
<PIN_PC4__SDMMC1_CD>;
slew-rate = <0>;
bias-pull-up;
};
};
pinctrl_sdmmc2_default: sdmmc2_default {
cmd_data {
pinmux = <PIN_PD3__SDMMC2_CMD>,
<PIN_PD5__SDMMC2_DAT0>,
<PIN_PD6__SDMMC2_DAT1>,
<PIN_PD7__SDMMC2_DAT2>,
<PIN_PD8__SDMMC2_DAT3>;
slew-rate = <0>;
bias-pull-up;
};
ck {
pinmux = <PIN_PD4__SDMMC2_CK>;
slew-rate = <0>;
bias-pull-up;
};
};
pinctrl_spdifrx_default: spdifrx_default {
pinmux = <PIN_PB0__SPDIF_RX>;
bias-disable;
};
pinctrl_spdiftx_default: spdiftx_default {
pinmux = <PIN_PB1__SPDIF_TX>;
bias-disable;
};
pinctrl_usba_vbus_det: usba_vbus_det {
pinmux = <PIN_PD11__GPIO>;
bias-disable;
};
pinctrl_usbb_vbus_det: usbb_vbus_det {
pinmux = <PIN_PC12__GPIO>;
bias-disable;
};
pinctrl_usba_vbus_en: usba_vbus_en {
pinmux = <PIN_PB2__GPIO>;
bias-disable;
};
pinctrl_usbb_vbus_en: usbb_vbus_en {
pinmux = <PIN_PC11__GPIO>;
bias-disable;
};
pinctrl_usbc_vbus_en: usbc_vbus_en {
pinmux = <PIN_PC6__GPIO>;
bias-disable;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_pwm2_default &pinctrl_mikrobus2_pwm3_default>;
status = "disabled"; /* Conflict with leds. */
};
&rtt {
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
};
&sdmmc0 {
bus-width = <8>;
non-removable;
vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&vldo1>;
mmc-ddr-1_8v;
cap-mmc-highspeed;
cap-mmc-hw-reset;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
};
&sdmmc1 {
bus-width = <4>;
vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&vdd_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "okay";
};
&sdmmc2 {
bus-width = <4>;
no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc2_default>;
};
&shdwc {
debounce-delay-us = <976>;
microchip,lpm-connection = <&gmac1 &main_xtal>;
input@0 {
reg = <0>;
};
};
&spdifrx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdifrx_default>;
status = "okay";
};
&spdiftx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdiftx_default>;
status = "okay";
};
&tcb0 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&usb0 {
atmel,vbus-gpio = <&pioA PIN_PD11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus_det>;
phys = <&usb_phy0>;
phy-names = "usb";
status = "okay";
};
&usb1 {
atmel,vbus-gpio = <&pioA PIN_PC12 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbb_vbus_det>;
phys = <&usb_phy1>;
phy-names = "usb";
status = "disabled";
};
&usb2 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioA PIN_PC11 GPIO_ACTIVE_HIGH
&pioA PIN_PC6 GPIO_ACTIVE_HIGH
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbb_vbus_en &pinctrl_usbc_vbus_en>;
phys = <&usb_phy1>, <&usb_phy2>;
phy-names = "usb", "usb";
status = "okay";
};
&usb3 {
status = "okay";
};
&usb_phy0 {
status = "okay";
};
&usb_phy1 {
status = "okay";
};
&usb_phy2 {
status = "okay";
};
&vddout25 {
vin-supply = <&vdd_3v3>;
status = "okay";
};
core/arch/arm/dts/fsl-lx2160a.dtsi
View file @ a5442c30
...@@ -416,6 +416,12 @@ ...@@ -416,6 +416,12 @@
reg = <0x00000000 0x80000000 0 0x80000000>; reg = <0x00000000 0x80000000 0 0x80000000>;
}; };
memory@2080000000 {
// DRAM space - 1, size : 126 GB DRAM
device_type = "memory";
reg = <0x00000020 0x80000000 0x0000001F 0x80000000>;
};
ddr1: memory-controller@1080000 { ddr1: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller"; compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>; reg = <0x0 0x1080000 0x0 0x1000>;
......
core/arch/arm/dts/sama5d2.dtsi
View file @ a5442c30
...@@ -737,6 +737,36 @@ ...@@ -737,6 +737,36 @@
secure-status = "okay"; secure-status = "okay";
}; };
sfc: sfc@f804c000 {
compatible = "atmel,sama5d2-sfc";
reg = <0xf804c000 0x64>;
read-only;
status = "disabled";
secure-status = "okay";
#address-cells = <1>;
#size-cells = <1>;
sfc_dr0: cell@20 {
reg = <0x20 0x20>;
};
sfc_dr1: cell@24 {
reg = <0x24 0x20>;
};
};
die_id: die_id {
compatible = "optee,nvmem-die-id";
nvmem-cells = <&sfc_dr0>;
nvmem-cell-names = "die_id";
};
huk: huk {
compatible = "optee,nvmem-huk";
nvmem-cells = <&sfc_dr1>;
nvmem-cell-names = "hw_unique_key";
};
i2s0: i2s@f8050000 { i2s0: i2s@f8050000 {
compatible = "atmel,sama5d2-i2s"; compatible = "atmel,sama5d2-i2s";
reg = <0xf8050000 0x100>; reg = <0xf8050000 0x100>;
......
core/arch/arm/dts/sama7g5-pinfunc.h 0 → 100644
View file @ a5442c30
This diff is collapsed.
core/arch/arm/dts/sama7g5.dtsi 0 → 100644
View file @ a5442c30
This diff is collapsed.
core/arch/arm/dts/stm32mp13-pinctrl.dtsi
View file @ a5442c30
...@@ -27,13 +27,13 @@ ...@@ -27,13 +27,13 @@
uart4_pins_a: uart4-0 { uart4_pins_a: uart4-0 {
pins1 { pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ pinmux = <STM32_PINMUX_NSEC('D', 6, AF8)>; /* UART4_TX */
bias-disable; bias-disable;
drive-push-pull; drive-push-pull;
slew-rate = <0>; slew-rate = <0>;
}; };
pins2 { pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ pinmux = <STM32_PINMUX_NSEC('D', 8, AF8)>; /* UART4_RX */
bias-disable; bias-disable;
}; };
}; };
......
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